1. Field of the Invention
The present invention relates generally to a color information display apparatus for use with a receiving apparatus for a character broadcast such as a teletext or the like, and is directed more particularly to a read-out circuit for a display memory.
2. Description of the Prior Art
It has been proposed to use a character multiplexed television broadcast in which various information, such as news, weather forecast, reports and the like, are broadcast by utilizing the vertical blanking period of the television broadcast.
For the character broadcast, there exists a code transmission system, pattern transmission system or combination of these two systems. As an example, the pattern transmission system will now be explained with reference to FIGS. 1 to 3, each of which shows an information format for such system.
In this example, as shown in FIG. 1, picture elements of 248 dots form one horizontal line, 204 horizontal lines thereof form one page, and one page forms the picture on the screen. In this case, however, one picture element takes a binary value of "1" or "0", and the picture elements of 8 dots.times.12 dots (lines) are designated as one sub-block. Thus, one page consists of 31.times.17 sub-blocks, and color is indicated for each sub-block unit. Further, the number of pages is selected to be, for example, about 100 pages, and the data of 100 pages is repeatedly broadcast.
As shown in FIG. 2A, the data signal is broadcast as a serial digital signal within the 20th horizontal period (during an odd field period) and the 283rd horizontal period (during an even field period) of the vertical blanking period, and as to any desired page each page of the data signal is broadcast as follows:
As shown in FIG. 3, a page control packet PP is broadcast or fed within the first field period. As shown in FIG. 2B, this packet PP comprises, in the header region of 48 bits of the horizontal period, a clock signal CK, a framing code signal FC showing the start position of the following signal and other control signals, and also in the data area of 248 bits of the horizontal period a page control signal which shows to which page the data signal belongs and the like.
Within the second field period, a line control packet LP is fed. As shown in FIG. 2C, this line control packet LP comprises, in the data area, a line code LC showing at which lines of the sub-blocks the following 12 packets are located and color codes for indicating the colors of the respective sub-blocks for each sub-block unit. The color codes consist of 4 bits for each sub-block and each designates the color thereof.
Further, during the 3rd to 14th field periods, 12 pattern data packets DP are sequentially fed. As shown in FIG. 2D, the packets DP each comprise in one line (31 sub-blocks) the picture elements of the first to 12th lines in the data areas thereof. For example, the first pattern data packet DP fed during the third field period includes the picture elements in the first line in the respective sub-blocks, that is, in the first line sequentially in the data area thereof.
Accordingly, all picture elements and the color information thereof in the sub-blocks in the first line of one page are completed by the packets fed from the second field period to the 14th field period.
Similar to the above, the sub-blocks of any one line are fed by the packet LP of one line and 12 following pattern data packets DP.
Thus, when the picture elements of the 12th line of the 17th sub-block (in the vertical direction) are fed during the 222nd field period by the packet DP, the data of one page has been fed. During the field periods following the 223rd field period, the data of other pages are again fed starting from the page control packet PP sequentially. Accordingly, the data of one page is fed by one page control packet PP, 17 line control packets LP and 204 (17.times.12) pattern data packets DP. In this case, 204 pattern data packets DP correspond to the picture elements of FIG. 1.
A prior art receiver for character broadcast with the above format is constructed as shown in, for example, FIG. 4.
In FIG. 4, a video signal system 10 includes a tuner 11, a VIF (video intermediate frequency) amplifier 12 and a video detecting circuit 13. Upon receiving an ordinary or conventional broadcast, the composite color video signal from video detecting circuit 13 is fed to a color signal reproducing circuit 14 from which three primary color signals R, G and B are derived. These three primary color signals R, G and B are supplied through a switching circuit 15 to a color cathode ray tube 16 to be reproduced as a color image on a display screen thereof.
In FIG. 4, a reproducing system 20 for the character broadcast which uses a microcomputer is provided. In particular, system 20 includes a CPU central processing unit) 21 which, for example, processes 8-bit parallel data, a ROM (read only memory) 22 in which the program for receiving the character broadcast is written and a RAM (random access memory) 23 for the work area. The above elements are connected through a data bus 24 and an address bus 25, which are, in turn, connected to an interface 26.
Further, in FIG. 4, a buffer memory 33 having a storage capacity for one packet, and display memories 34 and 35 each having a storage capacity for one page are provided. In this case, memory 34 is a pattern memory for storing the pattern data and memory 35 is a color memory for storing the color code information. A key board 41 and a timing signal generating circuit 42 are also provided. The key board 41 comprises a key (switch) for changing over between the normal broadcast receiving mode and the character broadcast receiving mode, a key for selecting desired pages and so on. The output from key board 41 is fed to interface 26 and also to timing signal generating circuit 42. Timing signal generating circuit 42 is formed of a synchronous separating circuit, a PLL (phase locked loop), a logic circuit and the like, and is supplied with the video signal from video detecting circuit 13 to generate various signals synchronized with the video synchronizing pulses and clock signal CK, for example, a clock pulse synchronized with clock signal CK and with a frequency of 1/8 (one-eighth) of the frequency thereof, and so on. A flag signal showing the vertical scanning period and the vertical fly-back period is supplied from generating circuit 42 to CPU 21 which, in turn, supplies flag signals representing the completion of various processes to generating circuit 42.
Further, address counters 43, 44 and 45 are provided. Address counter 43 serves as a write address counter which will designate the address of memory 33 during the write-in mode and is supplied with the clock pulse from generating circuit 42 as a count input and also with a clear pulse synchronized with the horizontal synchronizing pulse, so that the count value of counter 43 is incremented one count during the header and data periods of the packet, for every 8 bits of the header and data information. Further, counters 44 and 45 are respectively read address counters which will designate the address of memories 34 and 35 during the read-out mode, respectively. The read address counter 44 is supplied with the horizontal synchronizing pulse from generating circuit 42 as a count input and also with a clear pulse synchronized with the vertical synchronizing pulse, so that the count value of counter 44 is incremented by one for every horizontal period starting from the horizontal period when the most significant line of the character of the character broadcast is displayed. Further, read address memory 45 is supplied with the clock pulse from generating circuit 42 as a count input and also with a clear pulse synchronized with the horizontal synchronizing pulse, so that the count value of counter 45 is incremented by one for at every bit of the clock pulse starting from the time when the dot at the left end of the character of the character broadcast is displayed.
The video signal from video detecting circuit 13 is also supplied to a shift register 31 of the serial input-parallel output type in which the packet is converted from a serial signal to a parallel signal for every 8 bits and then supplied to a gate circuit (3-state buffer) 32. The counter 44 produces a pulse P.sub.44 which is at logic level "1" during the horizontal period (horizontal period of the 20th or 283rd lines) within which the packet is fed, and this pulse P.sub.44 is supplied to gate circuit 32 as a control signal. Thus, the packet signal is delivered as an 8 bit in parallel signal to data bus 24.
At this time, pulse P.sub.44 is also supplied to CPU 21 as a hold signal, so that CPU 21 is operated in a holding state during the horizontal feed period of the packet. The pulse P.sub.44 is further applied to a change-over gate 46 as a control signal, whereby the output from counter 43 is supplied through change-over gate 46 to memory 33 as an address signal. Accordingly, the packet signal is transferred as an 8 bit in parallel signal from register 31 through data bus 24, but not through CPU 21, to memory 33 by DMA (direct memory addressing). At this time, since the address of memory 33 is incremented one address counter 43 for every 8 clock pulses, the packet signal is written in memory 33 for every 8 bits.
After the horizontal period of the packet is completed, pulse P.sub.44 is at logic level "0" (P.sub.44 ="0") and register 31 is disconnected from data bus 24 by gate 32 which is then in its opened position. At this time, the holding state of CPU 21 is released, while address bus 25 is connected to memory 33 through change-over gate 46.
Consequently, data from memory 33 is processed by CPU 21 in accordance with the program stored in ROM 22 and it is determined whether the data is data of a desired page input by key board 41 or not from the received page control signal. When it is not that of the desired page, the data is neglected.
The above operation is repeated at every field until the packet PP of the desired page is received.
When the data from memory 33 is the packet PP of the desired page, the following operation will be carried out. Although the packets fed during the successive 221 field periods are desired or necessary packets, when the packet LP following the packet PP is fed, the packet LP is written in memory 33 by DMA. After the packet LP has been completely written thereinto and the holding state of CPU 21 is released, the data from memory 33 is processed by CPU 21 and the color code information is read out from memory 33. This color code information is then written in memory 35 through data bus 24, and is carried out during the same vertical fly-back period. The address bus 25 is connected to memory 35 through a change-over gate 47, which is supplied with the control signal from generating circuit 42, while the address of memory 35 is designated by CPU 21.
Further, when the next packet DP is fed following the packet LP, the packet DP is also written in memory 33 through DMA. Then, by processing by CPU 21, only the pattern data is transferred from memory 33 to memory 34 during the vertical fly-back period. The address of memory 34 is also designated by CPU 21.
When the packets LP and DP of the desired page are fed as set forth above, they are stored once in memory 33 by DMA. Then, necessary data is transferred therefrom to memories 34 and 35 by CPU 21 and written therein.
After the data of the last packet DP of the desired page is transferred to memory 34, CPU 21 returns to the waiting state to await a desired page again.
During the vertical scanning period, a control signal is supplied from generating circuit 42 to change-over gate 47 and the outputs from counters 44 and 45 are supplied through change-over gate 47 to memories 34 and 35 as the address signals for read-out. Then, the address in the vertical direction is designated by the output of counter 44 and the address in the horizontal direction is designated by the output of counter 45, so that the color code information and the pattern data stored in memories 34 and 35 are read out simultaneously.
The pattern data read out from memory 34 is supplied to a shift register 36 of the parallel input to serial output type to be converted from a parallel signal to a serial signal. This serial signal is, in turn, supplied to a color generator 37 to which the color code information read out from memory 35 is also supplied, so that data of three primary color signals R, G and B are applied to switching circuit 15 from color generator 37. At this time, the control signal is supplied from generating circuit 42 to switching circuit 15 so that the latter is connected to color generator 37. Accordingly, the desired page of the character broadcast is displayed on receiver 16, that is, the character broadcast is received by the receiver shown in FIG. 4.
With the above prior art receiver, much of the area (address) in each of memories 34 and 35 is not used, and is therefore entirely useless. This will be explained with reference to FIG. 5 which shows the practical relation of the connection between memories 34 and 35 and address counters 44 and 45 of the prior art embodiment shown in FIG. 4. Since the pattern data are processed as parallel 8 bit data, the pattern memory 34 is made of one 8-bit address, while since the color code information is 4 bits at a time, color memory 35 is made of one 4-bit address, respectively. Counter 44 consists of counters 441 and 442, while counter 45 consists of counters 451, 452 and 453, respectively. Color generator 37 is formed of a latch circuit 371 and a decoder 372.
Timing signal generating circuit 42 produces a clock pulse P.sub.c which is in synchronism with the clock signal CK and has a frequency the same as that of the clock signal CK, as shown in FIG. 6A. This pulse P.sub.c is fed to the octal or 8-bit counter 451 which is also supplied with an enable signal from generating circuit 42 only during the display period to deliver an output C of 2.sup.2 bits, as shown in FIG. 6B, and a carry output CO, as shown in FIG. 6C. The pulse P.sub.c is also fed to the 31-bit counter 452 which is also supplied with the carry signal CO from counter 451 as an enable signal. Accordingly, the count value of counter 452 is incremented by one only during the pattern display period for every 8 bits of the pulse P.sub.c, as shown in FIG. 6D.
Outputs A, B, C, D and E from counter 452 are supplied to memory 34 as its lower addresses A.sub.0, A.sub.1, A.sub.2, A.sub.3 and A.sub.4. Accordingly, the lower addresses A.sub.0 to A.sub.4 of memory 34 are incremented by one during the pattern display period for every 8 bits of the pulse P.sub.c, as shown in FIG. 6D. In other words, the lower addresses A.sub.0 to A.sub.4 of memory 34 are varied periodically at the horizontal period in correspondence with the horizontal scanning of the picture screen (page).
Further, generating circuit 42 produces a pulse P.sub.h which is synchronized with the horizontal synchronizing pulse and has the same frequency therewith, as shown in FIG. 7A, and an enable signal only during the display period. The pulse P.sub.h and the enable signal are supplied to 204-bit counter 453 whose count outputs A . . . H are applied to memory 34 at its higher addresses A.sub.5, A.sub.6, . . . A.sub.12. Accordingly, the count value of counter 453 is incremented by one for every pulse P.sub.h during the pattern display period, as shown in FIG. 7B. Therefore, the higher addresses A.sub.5 to A.sub.12 of memory 34 are incremented by one in correspondence therewith, that is, the higher addresses A.sub.5 to A.sub.12 of memory 34 are periodically varied in response to the vertical scanning of the picture screen at the vertical period.
The output C of counter 451 is supplied to pattern memory 34 as a chip select signal CS so that the data of the address corresponding to the scanning position of the picture screen is read out from memory 34. The outputs D.sub.0, D.sub.1, . . . D.sub.7 of memory 34 are fed to shift register 36 which is also supplied with the carry output CO from counter 451 as a load signal L and with the clock pulse P.sub.c from generating circuit 42. Thus, register 36 generates in series the pattern data in correspondence with the scanning position of the picture screen.
The outputs A to E of counter 452 are also supplied to memory 35 as its lower addresses A.sub.0, A.sub.1, . . . A.sub.4. The pulse P.sub.h is also supplied to 17-bit counter 442 and to 12-bit counter 441, whose carry output CO is applied to the former as an enable signal. Outputs A, B, . . . E of counter 442 are applied to memory 35 at its higher addresses A.sub.5 to A.sub.9. The output C from the counter 451 is supplied to memory 35 as a chip select signal CS.
Thus, the count value of counter 442 is varied in correspondence with the horizontal scanning of the picture screen and is also varied every 12 horizontal periods, so that the address of memory 35 is varied at every sub-block in correspondence with the scanning of the picture screen and the color code information of each sub-block at the address is read out from memory 35.
The outputs D.sub.0 to D.sub.3 of memory 35 are applied to latch circuit 371 which is also supplied with the carry output CO of counter 451 as the latch signal therefor and with the clock pulse P.sub.c from generating circuit 42. Thus, from latch circuit 371 derived are the 4-bit color codes corresponding to the sub-block at the scanning position of the picture screen.
The pattern data from shift register 36 and the color code information from latch circuit 371 are supplied to decoder 372 from which three primary color signals R, G and B are derived.
In the above case, since the number of picture elements in one page is 284.times.204 dots and one dot is represented by one bit, memory 34 requires the following capacity: EQU 248.times.204=50592 (bits)
Further, since the color information is designated for each sub-block unit and each color code is represented by 4 bits, memory 35 requires the following capacity: EQU 31.times.17.times.4=2108 (bits)
However, memories with the above capacities are not conventionally sold memories. Therefore, for memory 34, a memory with the following capacity is used: EQU 65536 bits=8 K bytes
and as for memory 35, a memory with the following capacity is used: EQU 4096 bits=4.times.1 K bits
Accordingly, in memory 34, the following area (address) capacity is not used: EQU (65536-50592/65536).times.100.congruent.23 (%)
and in memory 35, the following area (address) capacity is not used: EQU (4096-2108/4096).times.100.congruent.49 (%)
so that there is much unused and wasted area.
As set forth above, although memories 34 and 35 have each a large capacity, much of the areas thereof are not actually used. Thus, the apparatus becomes expensive and the space factor therefore becomes poor.